Not really, HDL is HDL. At the end of the day, as long as you know what you want to do electrically then everything else is an exercise of translating that desire into VHDL, Verilog, or SystemVerilog. The only real hassle is creating test-benches and verification simulations. But at that point it’s discretionary towards the designer. A lot of tools coming from Intel, Xilinx, and Synopsys allow you to “black box” components. So a module written in VHDL can be incorporated into a design or test bench written in verilog and vis-versa. IMHO VHDL is still dominant because grey beard chief engineers throw a little hissy fit at design reviews when they learn the junior engineers did everything in verilog.
Is it such a hassle learning verilog if you know vhdl or vice versa?
Not really, HDL is HDL. At the end of the day, as long as you know what you want to do electrically then everything else is an exercise of translating that desire into VHDL, Verilog, or SystemVerilog. The only real hassle is creating test-benches and verification simulations. But at that point it’s discretionary towards the designer. A lot of tools coming from Intel, Xilinx, and Synopsys allow you to “black box” components. So a module written in VHDL can be incorporated into a design or test bench written in verilog and vis-versa. IMHO VHDL is still dominant because grey beard chief engineers throw a little hissy fit at design reviews when they learn the junior engineers did everything in verilog.